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CMOS MT90710 High-Speed Isochronous Multiplexer Preliminary Information
Features
* * * * * * * * * * Multiplexes eight 2.048 Mbit/s, ST-BUS links onto one serial high-speed 20.48 Mbit/s link 15.808 Mbit/s clear bandwidth transport Two 8 kbit/s and one 32 kbit/s oversampled signalling channels Embedded system timing and frame synchronization Frame buffer control signals generated on-chip Check-sum generated on multiplexed frame Remote synchronization indication Both master and slave timing mode operation On-chip reference generation for slave mode synchronization 4B/5B data encoding/decoding MT90710AP
ISSUE 1
January 1995
Ordering Information 84 Pin PLCC
0 C to +70 C
Description
The High-Speed Isochronous Multiplexer integrated circuit multiplexes up to eight Serial Telecom (ST-BUS) links onto a single 20 MHz loop to facilitate point-to-point data transport requirements. The MT90710 connects easily with standard Fiber Optic interfaces to form a complete electric to photonic conversion circuit. Optical transmission allows large bandwidth inter-shelf or, in distributed systems, inter-node communication by eliminating multiple data buses, cable inter-connect and attendant driver interfaces. The final result is a simple physical interface free of the radiated emissions and background noise susceptibility problems encountered in copper-wired environments.
Applications
* * * Fibre distributed sytems Backplane concentrators Local Area Networks (LANs)
STi0 STi5 STi6A STi6B STi7 DIN8K0 DIN8K1 DIN32K STo0 STo5 STo6A STo6B STo7 DOUT8K0 DOUT8K1 DOUT32K
TRANSMIT
To Transmit Driver Amplifier and Fiber Driver Transducer
TxDATA MODE0 MODE1 MODE2 F0b C4b E20i RLED LLED C20o POR RESET C4REFo C4o C40i
MUX
Overhead Checksum Frame Sync
4B/5B & NRZI Encode
PISO
Control
RECEIVE
DEMUX
Overhead Extract & Insert Error Check
Frame Alignment & Buffer External Memory Control
NRZI Decode Sync Detect 4B/5B Decode
From Receive Pin Diode, Pre-amp and Post-amp Circuits
SIPO RxDATA
Signals to External PLL
FBDATA0
FBADDR0
FBADDR7
FBDATA7
Figure 1 - Functional Block Diagram
5-3
FBWE
FBOE
MT90710
Preliminary Information
DOUT32K
RxDATA
TxDATA
MODE0
MODE1
MODE2
FBWE
FBOE
RLED
STo1
STo4
STo3
STo2
STo0
VDD
52
50
48
46
44
42
40
38
36
VDD POR FBDATA7 C4b FBDATA6 FBDATA5 DIN8K0 FBDATA4 DIN32K VDD VSS FBDATA3 STi0 FBDATA2 DIN8K1 FBDATA1 LLED FBDATA0 RESET IC VDD
54 56 58 60 62 64 66 68 70 72
34
VDD
VSS
VSS
F0b
NC
IC
32 30 28 26 24
NC VSS NC E20i STi7 STi6B STi6A STi5 STi4 STi3 VDD VSS STi2 STi1 C40i NC NC NC C4REFo C4o VSS
84 PIN PLCC
22 20 18 16 14
76
78
80
82
84
74
STo6B
STo6A
VSS
VSS
VDD
10
12
4
6
2
8
FBADDR0
FBADDR1
FBADDR2
FBADDR3
FBADDR4
FBADDR5
FBADDR6
FBADDR7
DOUT8K0
DOUT8K1
C20o
STo7
Figure 2 - Pin Connections
Pin Description
Pin # 1 2 3 Name VSS VDD STo7 Description Power Supply Ground. Nominally 0 volts. Positive Power Supply. Nominally 5 volts. Serial, 32 Channel, 2.048 Mb/s Link 7 (Output Type 3). Only channels 9 - 31 are available for user data transfer (1.474 Mb/s). Channels 0 - 8 (0.576 Mb/s) are reserved for access to fiber overhead information. Output is active only when the receiver detects the synchronization pattern on RxDATA input stream; output is high impedance during loss of synchronization. Asynchronous 8 kHz Signal 0 (Output Type 3). Sourced from the far-end DIN8K0 input. Asynchronous 8 kHz Signal 1 (Output Type 3). Sourced from the far-end DIN8K1 input. 20.48 MHz Clock (Output Type 3). Derived from transmit PLL 40.96 MHz clock divided by 2 (see pin 18). Made available for system use. No Internal Connection. Frame Buffer RAM Address Bit 7 (Output Type 2). Serial, 32 Channel, 2.048 Mb/s Link 6A (Output Type 3). Output is active only when the receiver detects the synchronization pattern on RxDATA input stream; output is high impedance during loss of synchronization.
4 5 6 7 8 9
DOUT8K0 DOUT8K1 C20o NC FBADDR7 STo6A
5-4
STo5
VDD
NC
NC
Preliminary Information
Pin Description
Pin # 10 Name STo5 Description
MT90710
Serial, 32 Channel, 2.048 Mb/s Link 5 (Output Type 3). Output is active only when the receiver detects the synchronization pattern on RxDATA input stream; output is high impedance during loss of synchronization. Positive Power Supply. Nominally 5 volts. Power Supply Ground. Nominally 0 volts. 4.096 MHz Clock (Output Type 3). Used by the transmit PLL. This clock is the input C40i (40.96MHz, see pin 18) master clock divided by 10 (inverted) and is fed back to the external PLL circuit as a reference. 4.096 MHz Reference Clock (Output Type 3). Used by transmit PLL. When in controller mode this clock is derived from the system C4b (4.096 MHz) clock input (see pin 57). When in peripheral mode this clock is extracted from the receive data on the fiber port. No Internal Connection. Transmit 40.96 MHz Clock (Input Type 2). Derived from the transmit PLL. This is the master clock used by the device. Serial, 32 Channel, 2.048 Mb/s Link 1 (Input Type 1). Serial, 32 Channel, 2.048 Mb/s Link 2 (Input Type 1). Power Supply Ground. Nominally 0 volts. Positive Power Supply. Nominally 5 volts. Serial, 32 Channel, 2.048 Mb/s Link 3 (Input Type 1). Serial, 32 Channel, 2.048 Mb/s Link 4 (Input Type 1). Serial, 32 Channel, 2.048 Mb/s Link 5 (Input Type 1). Serial, 32 Channel, 2.048 Mb/s Link 6A (Input Type 1). Serial, 32 Channel, 2.048 Mb/s Link 6B (Input Type 1). Serial, 32 Channel, 2.048 Mb/s Link 7 (Input Type 1). Only channels 9 - 31 are available for user data transfer (1.472 Mb/s). Data input on channels 0 - 8 (0.576 Mb/s) is ignored by the device. This bandwidth is reserved for fiber overhead information. Receiver 20.96 MHz Clock (Input Type 2). Extracted clock from the receive data stream. Divided internally by 5 and phase corrected to frame synch pattern to produce internal 2.048 MHz data clock for parsing the receive STi streams. No Internal Connection. Power Supply Ground. Nominally 0 volts. No Internal Connection. Positive Power Supply. Nominally 5 volts. No Internal Connection. Receive 4B/5B, NRZI Encoded Serial Data (Input Type 1). "Remote Sync" LED Driver (Open Collector, Output Type 3). Drives the "Remote Sync" LED on/off at approximately a 4 Hz rate when the remote interface is not synchronized. Active only when the local interface is synchronized. Frame Buffer Ram Enable (Output Type 2). Generates a low going strobe during valid RAM read access.
5-5
11 12 13
VDD VSS C4o
14
C4REFo
15,16, 17 18 19 20 21 22 23 24 25 26 27 28
NC C40i STi1 STi2 VSS VDD STi3 STi4 STi5 STi6A STi6B STi7
29
E20i
30 31 32 33 34 35 36
NC VSS NC VDD NC RxDATA RLED
37
FBOE
MT90710
Pin Description
Pin # 38 39 40 41 Name MODE2 MODE1 MODE0 STo0 Description Operating Mode Select 2 (Input Type 1). See Table 1. Operating Mode Select 1 (Input Type 1). See Table 1. Operating Mode Select 0 (Input Type 1). See Table 1.
Preliminary Information
Serial, 32 Channel, 2.048 Mb/s link 0 (Output Type 3). Output is active only when receiver detects the synchronization pattern on RxDATA input stream; output is high impedance during loss of synchronization. Positive Power Supply. Nominally 5 volts. Power Supply Ground. Nominally 0 volts. Serial, 32 Channel, 2.048 Mb/s link 2 (Output Type 3). Output active only when receiver detects the synchronization pattern on RxDATA input stream; high impedance output during loss of synchronization. Serial, 32 Channel, 2.048 Mb/s link 3 (Output Type 3). Output active only when receiver detects the synchronization pattern on RxDATA input stream; high impedance output during loss of synchronization. Serial, 32 Channel, 2.048 Mb/s link 4 (Output Type 3). Output active only when receiver detects the synchronization pattern on RxDATA input stream; high impedance output during loss of synchronization. Frame Buffer RAM Write Enable (Output Type 2). Generates a low going strobe during valid RAM write access. Serial, 32 Channel, 2.048 Mb/s link 1 (Output Type 3). Output active only when receiver detects the synchronization pattern on RxDATA input stream; high impedance output during loss of synchronization. System 8 kHz Reference Frame Pulse (Bi-directional; Input and Output Types 3). When in controller mode this is an input accepting the system reference pulse. In peripheral mode this is an output supplying the system an 8 kHz reference frame pulse. Asynchronous 32 kHz Signal 1 (Open Collector, Output Type 3). Sourced from the far-end DIN32K input. Transmit 4B/5B, NRZI Encoded Serial Data (Output Type 3). Power Supply Ground. Nominally 0 volts. Internally Connected (Output Type 1). Drives continuous logic 1. Leave open circuit. Positive Power Supply. Nominally 5 volts. Power On Reset (Input Type 2). Active low. Frame Buffer Data Bit 7 (Bidirectional; Input Type 1 and Output Type 2). Data bit 7. 4.096 MHz Reference Clock (Bidirectional; Input and Output Types 3). Input used by PLL in controller mode and derived from the system. In peripheral mode this is an output supplying the system 4.096 MHz reference clock. Frame Buffer Data Bit 6 (Bidirectional; Input Type 1 and Output Type 2). Data bit 6. Frame Buffer Data Bit 5 (Bidirectional; Input Type 1 and Output Type 2). Data bit 5. Asynchronous 8 kHz Signal 0 (Input Type 1). Transmitted to the far-end DOUT8K0 output. Frame Buffer Data Bit 4 (Bidirectional; Input Type 1 and Output Type 2). Data bit 4.
42 43 44
VDD VSS STo2
45
STo3
46
STo4
47 48
FBWE STo1
49
F0b
50 51 52 53 54 55 56 57
DOUT32K TxDATA VSS IC VDD POR FBDATA7 C4b
58 59 60 61
FBDATA6 FBDATA5 DIN8K0 FBDATA4
5-6
Preliminary Information
Pin Description
Pin # 62 63 64 65 66 67 68 69 70 Name DIN32K VDD VSS FBDATA3 STi0 FBDATA2 DIN8K1 FBDATA1 LLED Description
MT90710
Asynchronous 32 kHz Signal (Input Type 1). Transmitted to the far-end DOUT32K output. Positive Power Supply. Nominally 5 volts. Power Supply Ground. Nominally 0 volts. Frame Buffer Data Bit 3 (Bidirectional; Input Type 1 and Output Type 2). Data bit 3. Serial, 32 Channel, 2.048 Mb/s Link 0 (Input Type 1). Frame Buffer Data Bit 2 (Bidirectional; Input Type 1 and Output Type 2). Data bit 2. Asynchronous 8 kHz Signal 1 (Input Type 1). Transmitted to the far-end DOUT8K1 output. Frame Buffer Data Bit 1 (Bidirectional; Input Type 1 and Output Type 2). Data bit 1. "Local Sync" LED Driver (Open Collector, Output Type 2). Drives the "Local Sync" LED on/off at approximately a 4 Hz rate when the local interface is not in synchronization. Frame Buffer Data Bit 0 (Bidirectional; Input Type 1 and Output Type 2). Data bit 0. Reset Control (Input Type 1). Internally Connected. Positive Power Supply. Nominally 5 volts. No Internal Connection. Power Supply Ground. Nominally 0 volts. Frame Buffer RAM Address Bit 0 (Output Type 2). Frame Buffer RAM Address Bit 1 (Output Type 2). Frame Buffer RAM Address Bit 2 (Output Type 2). Frame Buffer RAM Address Bit 3 (Output Type 2). Frame Buffer RAM Address Bit 4 (Output Type 2). Frame Buffer RAM Address Bit 5 (Output Type 2). Frame Buffer RAM Address Bit 6 (Output Type 2). Serial, 32 Channel, 2.048 Mb/s Link 6B (Output Type 3). Output active only when receiver detects the synchronization pattern on RxDATA input stream; high impedance output during loss of synchronization.
71 72 73 74 75 76 77 78 79 80 81 82 83 84
FBDATA0 RESET IC VDD NC VSS FBADDR0 FBADDR1 FBADDR2 FBADDR3 FBADDR4 FBADDR5 FBADDR6 STo6B
Notes: All unused inputs should be connected to logic high or low unless otherwise stated. All outputs should be left open circuit when not used. All output types are CMOS with CMOS logic levels (see DC Electrical Characteristics for Type drive capability). Input Type 1 has TTL compatible logic levels, Type 2 has CMOS compatible logic levels and Type 3 has TTL Schmitt trigger compatible logic levels (see DC Electrical Characteristics).
Overview
The MT90710 multiplexes multiple Serial Telecom (ST-BUS timing, Figure 7) links onto a single 20 MHz loop to facilitate point-to-point data transport requirements. The MT90710 connects easily with standard Fiber Optic interfaces to form a complete electric to photonic conversion circuit. Optical
transmission allows large bandwidth inter-shelf or, in distributed systems, inter-node communication by eliminating multiple data busses, cable inter-connect and the attendant driver interfaces. The final result is a simple physical interface free of the radiated emissions and background noise susceptibility problems encountered in copper-wired environments.
5-7
MT90710
Frame Pulse
Preliminary Information
Fiber Timeslot
255 0 1 2 3 4 5 6 7 8 9 .......... 246 247 248 249 250 251 252 2
Channel Assignment ST7 Ch0 ST6 Ch0 ST5 Ch0 ST4 Ch0 ST3 Ch0 ST2 Ch0 ST1 Ch0 ST0 Ch0 ST7 Ch1 ST6 Ch1
4B/5B Encoded Data Bit Assignment Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Figure 3 - Fiber Timeslot Assignment The MT90710 provides 15.808 Mb/s clear channel, user bandwidth in both transmit and receive directions. In addition, two 8 kHz sampled signals and one 32 kHz sampled signal are encoded and transported over the loop as additional user bandwidth. These asynchronous signals, in combination with overhead information and clear channel bandwidth produce an aggregate data rate of 16.384 Mb/s. After encoding (4B/5B) the final transmitted baud rate is 20.48 Mbaud. Once compiled, the contents of the transmit data bandwidth is first 4B/5B encoded, then NRZI encoded before it is applied to the transmit fiber interface driver via TxDATA. 4B/5B ensures that the NRZI encoded data will contain a minimum of two transitions per baud. This is sufficient to allow the far end to extract the embedded clock information. As a result of 4B/5B encoding the information bandwidth of 16.384 Mb/s increases to a total baud rate of 20.48 MBaud/s at the fiber interface. Incoming ST-BUS link data is latched at the mid-bit position of the internal timeslot. Since there is a phase difference between the internal and external timeslots, due to the operation of the PLL, latching occurs at approximately the 3/4 bit position of the external timeslot when in Controller mode. In Peripheral mode data is latched at the midpoint of the timeslot. Asynchronous signals DIN8K0-1 are sampled once per frame (8,000 times per second) and are intended to convey relatively static information where a state transition is not time critical enough that a resolution of one frame is detrimental. Asynchronous signal DIN32K is sampled four times per frame (32,000 times per second) and may be used to transport data at a higher rate than the other two asynchronous inputs. As an example, this sampling rate is sufficient to support 19.2K Baud RS-232 signals (TTL levels) so that remote programming or loop maintenance may be performed.
Transmit
The transmit data interface consists of nine ST-BUS input links and three asynchronously sampled input signals. These are STi0 - STi5, STi6A and STi6B, STi7, DIN8K0, DIN8K1 and DIN32K. Six ST-BUS input links, STi0-5, each provide 2.048 Mb/s transparent transmission bandwidth. With ST6MUX Mode disabled STi6A is also a 2.048 Mb/s link while STi6B is not used (see ST6MUX description). The first nine channels of the STi7 input are ignored leaving the remaining 23 channels for user bandwidth. This allows a total of 15.808 Mb/s clear bandwidth for application use. The first nine (576 kb/s) channels of STi7 are made available for transmitting the three asynchronous signals combined with fiber overhead information. This overhead is automatically compiled in the transmit interface and inserted into these timeslots for transmission over the fiber interface. Overhead information includes a frame synchronization byte, an error count and a checksum calculated on the previous frame of transmitted data.
5-8
Preliminary Information
MT90710
ST-BUS input data latched here
C20o
(Pin 6)
Bit Cell
C4o
(Pin 13)
122 ns
FBOE
170.8ns 48.8ns
FBWE
FBADDR
WR ADDR
RD ADDR
WR ADDR
RD ADDR
FBDATA
RD
WR
Figure 4 - Frame Buffer Memory Typical Timing
Receive
The 4B/5B and NRZI encoded data from the receive fiber interface is NRZI decoded and the frame synchronization information is extracted. After 4B/5B decoding the remaining data is frame aligned either to the system frame pulse (when in Controller Mode) or to the extracted frame pulse (when in Peripheral Mode). After alignment, the received data package is disassembled into the clear channel ST-BUS streams, the asynchronous signals and the overhead/status information. When ST6MUX mode is disabled, received 15.808 Mb/s bandwidth is made available on STo0-STo6A and the last 23 channels of STo7. The asynchronous signals are presented on DOUT8K0, DOUT8K1 and DOUT32K while the received overhead information, as well as local status information, is presented on ST07 in channels 0 to 7.
receive data interface when it's in peripheral mode. Switching between these two primary references is automatic and under the control of the MODE0-2 pins. The selected reference is fed to the external PLL from the C4REFo output pin. The MT90710 also divides the 40.96 MHz master clock by ten and supplies this secondary reference to the external PLL on C4o for comparison to the primary reference. The PLL creates a 40.96 MHz master clock from a 4.096 MHz reference by multiplying by 10 and attenuates jitter present on the extracted reference. The master clock is divided down to create internal clocks, external ST-BUS clocks (when in peripheral mode) and timeslot counters. Control signals are also created for the transmitter and receiver. The transmitter timeslot counter is synchronized to the backplane frame pulse while the receiver timeslot counter is sync to the extracted synchronization pulse.
Control
An external, 40.96 MHz PLL provides the master clock (C40i) for the MT90710. This PLL uses either the system's C4b clock (pin 57) for reference when it's in controller mode or the extracted clock from the
Frame Buffer
To re-align the received data from the fiber interface to the system, or node, a frame reference buffer is
5-9
MT90710
required. This is implemented using an external 8x8 static RAM (35 ns). Only 256 bytes are used of the 8K total. RAM address and data (FBADDR0-7 and FBDATA0-7) signals are generated along with an output enable strobe (FBOE) and a write enable strobe (FBWE). ST-BUS Interface
Preliminary Information
The first nine STo7 channels are reserved for overhead information: STo7 Channel 0 1 2 3 4 5 6 7 8 Function not available not available Reserved Local error count (most significant byte) Local error count (least significant byte) Reserved Remote error count (most significant byte) Remote error count (least significant byte) synchronization detect (see STo7 channel 8 definition)
Mode # Mode 2 Mode 1 Mode 0 0 1 2 3 4 5 6 7 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
ST6MUX
Configuration
ENABLED CONTROLLER ENABLED not used PERIPHERAL not used
DISABLED CONTROLLER not used not used not used DISABLED not used not used not used PERIPHERAL
Table 1 - Operational Mode Select
STo7 Channel 8 Definition:
B7 B6 Fiber Interface Eight of the 256 fiber channels are reserved for overhead information. These are fiber channels: Channel # Function 0 Frame Alignment 8 Asynchronous signal transfer and synchronization detect 16 Checksum of previous frame 24 Reserved 32 Reserved 40 Reserved 48 Remote error count most significant byte 56 Remote error count least significant byte B5, B4, B3 B2, B1, B0 remote receiver is in frame synch when logic 1 Local receiver is in frame synch when logic 1 Reserved Reserved
Overhead Information
ST6MUX
ST-BUS to Fiber When ST6MUX is enabled the STi6A and STi6B input streams are alternately multiplexed onto the fiber link. (i.e., only half of the bandwidth of each link is utilized). The transmit pattern at the fiber interface is:
STi6A-Chan0,STi6B-Chan1,STi6A-Chan2,STi6B-Chan3,..., STi6B-Chan29,STi6A-Chan30,STi6B-Chan31
Multiplexed Stream
STo6A Data from STi6A STo6B Data from STi6B
Chan 0 Chan 0 Chan 1
Chan 1 Chan 0 Chan 1
Chan 2 Chan 2 Chan 3
Chan 3 Chan 2 Chan 3
Chan 4 Chan 4 Chan 5
Chan 5 Chan 4 Chan 5
..... ..... .....
Chan 28 Chan 28 Chan 29
Chan 29 Chan 28 Chan 29
Chan 30 Chan 30 Chan 31
Chan 31 Chan 30 Chan 31
Table 2 - ST6MUX Channel Assignment
5-10
Preliminary Information
MT90710
CORRECT SYNC SET SYNC = LAST STATE
STATE 1
CORRECT SYNC SET SYNC = FALSE INCORRECT SYNC SET SYNC = LAST STATE
STATE 2
INCORRECT SYNC SET SYNC = TRUE
CORRECT SYNC SET SYNC = TRUE
STATE 0
INCORRECT SYNC SET SYNC = FALSE
STATE 3
INCORRECT SYNC SET SYNC = FALSE CORRECT SYNC SET SYNC = TRUE
Figure 5 - State Diagram approximately a 4 Hz rate when the far-end is out of synchronization but the near-end is synchronized. If the near-end is not synchronized this output is inactive. The open collector LLED output (pin 70) will cause an LED, pulled up to +5 volts, to flash at approximately a 4 Hz rate when the near-end is out of synchronization.
Fiber to ST-BUS When ST6MUX is enabled the STo6A and STo6B output streams are comprised of the demultiplexed information received from the fiber link. The received data is duplicated on two channels since the ST-BUS channels support twice the bandwidth of the data from the incoming fiber link. See Table 2. When ST6MUX is disabled the STi6B and STo6B ports are not operational. The STi6A and STo6A ports operate as clear 2.048 MHz links in the same manner as STi/o links 0 to 5.
Checksum Generator
Checksum =
255
Fiber Loop Synchronization
A receiver is declared in synchronization after detection of three consecutive frames containing a valid sync pattern. Once synchronized a receiver will lose sync if a valid sync pattern is not detected in two of four consecutive frames (refer to Figure 5).
DATA i + C i -1
i=1
LED Control
The open collector RLED output (pin 36) will cause an LED, pulled up to +5 volts, to flash at
Where i-1 is the carry out from the previous operation. The checksum is calculated on all 255 channels except on channel 0 where the frame synchronization code is transported. During this channel the previous checksum is stored and the register initialized for the next calculation.
5-11
MT90710
5-12
Checksum Framesynch 4B/5B and NRZI Encode Parallel-to-Serial Shift Serial-to-Parallel Shift NRZI Decode RxDATA Synch Detect 4B/5B Decode Error Check
Frame Alignment and External Buffer Controller
Transmit Amplifier and Fiber Transmitter
AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
S Y S T E M TxDATA
STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7
MUX
AAAA AAAA AAAA AAAA AAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
I N T E R F A C E Rx Clock Recovery and Bit Regeneration Clock Interface Frame Buffer Control Signals
STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7
DEMUX
Fibre Receiver and Amplifier
Transmit Clock PLL
Frame Buffer RAM 8K x 8
Preliminary Information
Figure 6 - Typical Fibre Interface Application
Preliminary Information
Absolute Maximum Ratings*
Parameter 1 2 3 4 DC Supply Voltage Input Voltage DC Input Current Storage Temperature Symbol VDD Vi Ii Tstg - 65 Min - 0.3 VSS - 0.3
MT90710
Max 7 VDD + 0.3 +/- 50 + 150 Units V V mA C
* Exceeding these figures may cause permanent damage. Functional operation under these conditions is not guaranteed.
Recommended Operating Conditions
Characteristics 1 2 Input Voltage Operating Temperature Sym VDD TOP Min 4.5 0 Typ Max 5.5 +70 Units V C Test Conditions
DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 Supply Current operating Sym IDD VIHT VILT VIHC VILC V+ VVH IIH/IIL VOH VOL IO1 IO4 IO12 IOZ Co Ci 7 1 4 12 20 20 20 3.7 0.4 0.8 0.5 150 0.7VDD 0.3VDD 2.0 2.0 0.8 Min Typ 230 Max 276 Units mA V V V V V V V A V V mA mA mA A pF pF Input Type 1 Input Type 1 Input Type 2 Input Type 2 Input Type 3 Input Type 3 Input Type 3 VDD=5.5V, VIN=VSS to VDD All output types @ max I All output types @ max I Output Type 1 Output Type 2 Output Type 3 VDD=5.5V, VIN=VSS to VDD Test Conditions
Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH voltage (CMOS) Input LOW voltage (CMOS) Positive threshold (schmitt) Negative threshold (schmitt) Hysteresis Input leakage current High level output voltage Low level output voltage Output Current
13 14 15
High impedance leakage Output capacitance Input capacitance
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
5-13
MT90710
AC Electrical Characteristics - ST-BUS Timing
Voltages are with respect to ground (VSS) unless otherwise stated.
Preliminary Information
Characteristics 1 2 3 4 5 6 7 8 9 Frame Pulse width Frame Pulse setup time Frame Pulse hold time STo delay Active to Active STi setup time STi hold time Clock period CK Input Low CK Input High
Sym tF0iW tF0iS tF0iH tDAA tSTiS tSTiH tC4i tCL tCH tr,tf
Min
Typ 244
Max
Units ns
Test Conditions
10 20 45 20 20 200 85 85 244 122 122
190 190 100
ns ns ns ns ns CL=150 pF
300 150 150 10
ns ns ns ns
10 Clock Rise/Fall Time
Timing is over recommended temperature & power supply voltages (VDD=5V10%, VSS=0V, TA=0 to 70C). Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
tF0iW F0i
2.0V 0.8V
tF0iH
2.0V
tC4i
tCH
tCL
C4i
0.8V
tF0iS
tf tr tDAA
STo
2.0V 0.8V
Ch. 31 Bit 0
Ch. 0 Bit 7
Ch. 0 Bit 6 tSTiH
Ch. 0 Bit 5
tSTiS
2.0V 0.8V
STi
Ch. 31 Bit 0
Ch. 0 Bit 7
Ch. 0 Bit 6
Ch. 0 Bit 5
Figure 7 - ST-BUS Timing
5-14

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